The present invention is directed to the processing of wafers, substrates or disks, such as silicon wafers, and more specifically to cluster tool systems and methods for processing wafers prior to device formation.
Wafers or substrates with exemplary characteristics must first be formed prior to the formation of circuit devices. In determining the quality of the semiconductor wafer, the flatness of the wafer is a critical parameter to customers since wafer flatness has a direct impact on the subsequent use and quality of semiconductor chips diced from the wafer. Hence, it is desirable to produce wafers having as near a planar surface as possible.
In a current practice, cylindrical boules of single-crystal silicon are formed, such as by Czochralski (CZ) growth process. The boules typically range from 100 to 300 millimeters in diameter. These boules are cut with an internal diameter (ID) saw or a wire saw into disc-shaped wafers approximately one millimeter (mm) thick. The wire saw reduces the kerf loss and permits many wafers to be cut simultaneously. However, the use of these saws results in undesirable waviness of the surfaces of the wafer. For example, the topography of the front surface of a wafer may vary by as much as 1-2 microns (μ) as a result of the natural distortions or warpage of the wafer as well as the variations in the thickness of the wafer across its surface. It is not unusual for the amplitude of the waves in each surface of a wafer to exceed fifteen (15) micrometers. The surfaces need to be made more planar (planarized) before they can be polished, coated or subjected to other processes.
FIG. 1 depicts a typical prior art method 10 for processing a silicon wafer prior to device formation. Method 10 includes a slice step 12 as previously described to remove a disc-shaped portion of wafer from the silicon boule. Once the wafer has been sliced, the wafer is cleaned and inspected (Step 14). Thereafter, an edge profile process (Step 16) is performed. Once the edge profile has been performed, the wafer is again cleaned and inspected (Step 18), and is laser marked (Step 20).
Next, a lapping process (Step 22) is performed to control thickness and remove bow and warp of the silicon wafer. The wafer is simultaneously lapped on both sides with an abrasive slurry in a lapping machine. The lapping process may involve one or more lapping steps with increasingly finer polishing grit. In another prior art method, a grinding process replaces the lapping procedure in FIG. 1. Problems incumbent with this process are further described in U.S. application Ser. No. 09/808,790, filed contemporaneously herewith, the complete disclosure of which is incorporated herein by reference.
The wafer is then cleaned (Step 24) and etched (Step 26) to remove damage caused by the lapping process. The etching process may involve placing the wafer in an acid bath to remove the outer surface layer of the wafer. Typically, the etchant is a material requiring special handling and disposal. Thereafter, an additional cleaning of the wafer (Step 28) is performed.
The prior art method continues with a donor anneal (Step 30) followed by wafer inspection (Step 32). Thereafter, the wafer edge is polished (Step 24) and the wafer is again cleaned (Step 36). Typical wafer processing involves the parallel processing of a multitude of wafers. Hence at this juncture wafers may be sorted, such as by thickness (Step 38), after which a double side polish process is performed (Step 40).
The wafers then are cleaned (Step 42) and a final polish (Step 44) is performed. The wafers are again cleaned (Step 46), inspected (Step 48) and potentially cleaned and inspected again (Steps 50 and 52). For epitaxial substrates, a poly or oxide layer is overlaid to seal in the dopants after inspection Step 52. At this point, the wafer is packed (Step 54), shipped (Step 56) and delivered to the end user (Step 58). Hence, as seen in FIG. 1 and as described above, typical wafer processing involves a lengthy, time consuming process with a large number of processing steps.
A number of deficiencies exist with the prior art method. As can be seen from even a precursory review of FIG. 1, the prior art method requires a large number of steps to transform a wafer slice into a substrate suitable for creating circuit devices. The large number of process steps involved negatively effects production throughput, requires a large production area, and results in high fabrication costs. Additionally, each of the steps in FIG. 1 are typically performed at individual process stations. The stations are not grouped or clustered together, and manual delivery of the wafers between stations is often used.
Additionally, the large production area required results in the need for a separate facility for the wafer processing described in FIG. 1 than for device formation on the wafer. To produce integrated circuits and other devices from the wafers, the wafers are packed, shipped and delivered to the appropriate fabrication facility. Upon receipt by the fabrication facility, the wafers must be received, unpacked, inspected and delivered to a wafer processing chamber for subsequent process steps necessary for device formation. These additional processing and delivering steps add to the complexity and cost of wafer processing prior to device fabrication. Unfortunately, to date, separate facilities are required due at least in part to the large area needed for FIG. 1 processing. As a result, small volume manufacturing of wafers is difficult.
In addition to the large number of process steps, at least some of the prior art steps themselves are slow or produce unacceptable results. For example, compared to a grinding process, the lapping process is slow and must be followed by careful cleaning and etching steps to relieve stresses before the wafer is polished. These additional steps cause the conventional method to be more expensive and time-consuming than methods of the present invention. Also, the etching process employed after the lapping step is undesirable from an environmental standpoint, because the large amount of strong acids used must be disposed of in an acceptable way.
Additional deficiencies in the current art, and improvements in the present invention, are described below and will be recognized by those skilled in the art.